In recent years, a carry look-ahead (CLA) circuit is widely adopted to improve arithmetic operation speed in an adder of a semiconductor integrated circuit (see, for example, Japanese Laid-open Patent Publication No. 6-35668 and Japanese Laid-open Patent Publication No. 8-123662). FIG. 10 is a diagram of a carry generation and propagation block (a block for generating a generate signal and a propagate signal for four bits) of a conventional CLA circuit. As depicted in the figure, the CLA circuit includes NAND gates 10 to 18, NOR gates 20 to 23, and NOT gates 30 to 39. A0 to A3 in the figure correspond to a first bit to a fourth bit of a first operand as an arithmetic operation target. B0 to B3 in the figure correspond to a first bit to a fourth bit of a second operand as an arithmetic operation target.
Signals output from the NOT gates 31, 33, 35, and 37 are represented as generate output signals G0 to G3 (Gn=An·B), respectively, and signals output from the NOT gates 30, 32, 34, and 36 are represented as propagate output signals P0 to P3 (Pn=An+Bn), respectively. A generate signal (GG) is calculated by GG=G3+P3·G2+P3·P2·G1+P3·P2·P1·G0. A propagate signal (GP) is calculated by GP=P3·P2·P1·P0. A carry is calculated by using the generate signal and the propagate signal.
For example, a carry obtained by adding up a 16-bit first operand and a 16-bit second operand is represented as CO (carry out). The carry CO can be calculated by CO=GG3+GP3·GG2+GP3·GP2·GG1+GP3·GP2·GP2·GG0+GP3·GP2·GP1·GP0·CI by using the generate signal and the propagate signal.
GG0 corresponds to generate signals of first bits to fourth bits of the first and second operands as an arithmetic operation targets. GG1 corresponds to generate signals of fifth bits to eighth bits of the first and second operands as arithmetic operation targets. GG2 corresponds to generate signals of ninth bits to twelfth bits of the first and second operands as arithmetic operation targets. GG3 corresponds to generate signals of thirteenth bits to sixteenth bits of the first and second operands as arithmetic operation targets.
GP0 corresponds to propagate signals of the first bits to fourth bits of the first and second operands as arithmetic operation targets. GP1 corresponds to propagate signals of the fifth bits to eighth bits of the first and second operands as arithmetic operation targets. GP2 corresponds to propagate signals of the ninth bits to twelfth bits of the first and second operands as arithmetic operation targets. GP3 corresponds to propagate signals of the thirteenth bits to sixteenth bits of the first and second operands as arithmetic operation targets. CI represents a carry from a low order digit.
Conventionally, a technology called pseudo carry is also used. In the pseudo carry, pseudo signals are used for the generate signal and the propagate signal of the CLA circuit explained with reference to FIG. 10, thereby reducing the number of inputs of gates to realize an increase in speed of a CLA circuit and a reduction in the number of transistors. FIG. 11 is a diagram of a carry generation and propagation circuit of a CLA circuit (a 4-bit CLA circuit) to which the pseudo carry is applied. As depicted in the figure, the CLA circuit includes NAND gates 40 to 47, NOR gates 50 to 54, and NOT gates 60 to 68.
Signals output from the NOT gates 61, 63, 65, and 67 are represented as generate output signals G0 to G3, respectively. Signals output from the NOT gates 60, 62, 64, and 66 are represented as propagate output signals P0 to P3, respectively. A pseudo generate signal (GG′) is calculated by GG′=G3+G2+P2·G1+P2·P1·G0. A pseudo propagate signal (GP′) is calculated by GP′=P2·P1·P0·P(n−1). A pseudo carry is calculated by using the pseudo generate signal and the pseudo propagate signal. If An and Bn depicted in FIG. 11 are least significant bits (when n is 0), a value of P(n−1) is 1.
A pseudo carry obtained by adding up a 16-bit first operand and a 16-bit second operand is represented as CO′. The pseudo carry CO′ can be calculated by CO′=GG3′+GP3′·GG2′+GP3′·GP2′·GG1′+GP3′·GP2′·GP1′·GG0′+GP3′·GP2′·GP0′·CI by using the generate signal and the propagate signal.
GG0′ corresponds to pseudo generate signals of the first bits to fourth bits of the first and second operands as arithmetic operation targets. GG1′ corresponds to pseudo generate signals of the fifth bits to eighth bits of the first and second operands as arithmetic operation targets. GG2′ corresponds to pseudo generate signals of the ninth bits to twelfth bits of the first and second operands as arithmetic operation targets. GG3′ corresponds to pseudo generate signals of the thirteenth bits to sixteenth bits of the first and second operands as arithmetic operation targets.
GP0′ corresponds to pseudo propagate signals of the first bits to fourth bits of the first and second operands as arithmetic operation targets. GP1′ corresponds to pseudo propagate signals of the fifth bits to eighth bits of the first and second operands as arithmetic operation targets. GP2′ corresponds to pseudo propagate signals of the ninth bits to twelfth bits of the first and second operands as arithmetic operation targets. GP3′ corresponds to pseudo propagate signals of the thirteenth bits to sixteenth bits of the first and second operands as arithmetic operation targets. CI represents a carry from a low order digit.
The carry CO can be calculated by an AND of the pseudo carry CO′ and a propagate output signal Pn for a most significant bit (CO=CO′·Pn; n is a digit of the most significant bit). For example, if a 16-bit pseudo carry CO′ and a 16-bit propagate output signal Pn are added up, the carry CO can be calculated by CO=CO′·P15(P15=A15+B15).
When FIG. 10 and FIG. 11 are compared, whereas the number of inputs of the NAND gate 18 at a first stage from the right in FIG. 10 is four, the number of inputs of the NAND gate 47 at a first stage from the right in FIG. 11 is reduced to three. Whereas the number of inputs of the NAND gate 15 at a second stage from the right in FIG. 10 is four, the number of inputs of the NAND gate 45 at a second stage from the right in FIG. 11 is reduced to three. In this way, it is possible to reduce the number of inputs of the gates and realize an increase in speed of the CLA circuit and a reduction in the number of transistors by using the pseudo carry.
Conventionally, the number of transistors of a CLA circuit is reduced and the number of stages of gates is reduced to realize an increase in speed of the CLA circuit by using an inverse logic. The inverse logic is a logic for generating inverted signals (XGG and XGP) of a generate signal and a propagate signal from inverted signals XGn and XPn of Gn and Pn ad using the inverted signals (XGG and XGP) as they are. FIG. 12 is a diagram of a carry generation and propagation block of a CLA circuit to which the inverse logic is applied.
As depicted in the figure, the CLA circuit includes NAND gates 70 to 77, NOR gates 80 to 84, and NOT gates 90 and 91. Signals output from the NAND gates 70 to 73 are represented as inverted generate signals XG0 to XG3, respectively. Signals output from the NOR gates 80 to 83 are represented as inverted propagate signals XP0 to XP3, respectively. An inverted signal of a generate signal (XGG; hereinafter, “inverted generate signal”) is calculated by XGG=XP3+XG3·XP2+XG3·XG2·XP1+XG3·XG2·XG1·XG0. An inverted signal of a propagate signal (XGP; hereinafter, “inverted propagate signal”) is calculated by XGP=XP3+XP2+XP1+XP0. The inverted generate signal XGG passes through the NOT gate 91 to change to the generate signal GG. The inverted propagate signal changes to the propagate signal GP in the NOR gate 84.
When FIG. 10 and FIG. 12 are compared, NOT gates corresponding to the NOT gates 30 to 37 depicted in FIG. 10 are deleted from the CLA circuit depicted in FIG. 12. Instead, a NOT gate 91 is added to the CLA circuit depicted in FIG. 12. In this way, it is possible to reduce the number of transistors and realize an increase in speed of the CLA circuit by using the inverse logic.
As explained above, when a generate signal is generated, it is possible to reduce the number of inputs in the gates by using the pseudo carry (see FIG. 11). However, the number of transistors increases when an addition result is generated by using a pseudo carry signal. Therefore, the pseudo carry signal (CO′) is converted into the normal carry signal (CO) and used (CO=CO′·Pn).
When the pseudo carry signal (CO′) is converted back into the normal carry signal (CO), an AND gate for taking AND of the pseudo carry signal (CO′) and the propagate output signal Pn of the most significant bit is required. Therefore, while the effect of reducing the number of transistors can be maintained, the number of stages increases and the advantage of an increase in speed of the CLA circuit is lost.
Further, when a multi-bit CLA circuit is configured by using the inverse logic, the NOT gate 91 (see FIG. 12) for resetting the polarity of an inverted generate signal is required. As a result, the number of gate stages cannot be reduced and an increase in speed of the CLA circuit cannot be efficiently performed.